Design-Reuse10 年
H.264 Baseline Encoder with ADI Blackfin DSP and Hardware Accelerators
In this paper, architecture and implementation of H.264/AVC baseline en coder for D1 resolution at 30fps using ADI Blackfin DSP and Hardware accelerators in FPGA is described. FPGA accelerators ...
Design-Reuse4 年
H.264 Baseline Decoder With ADI Blackfin DSP and Hardware Accelerators
In this paper, architecture and implementation of H.264/AVC baseline decoder for D1 resolution at 30fps using ADI Blackfin DSP and Hardware accelerators in FPGA is described. 1. Introduction There are ...