The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces. Control is ...

Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Memory Map address, and signals a DMA Controller to ...