The paper describes how, with a SOPC (System on a Programmable Chip) architecture embedded with a 32-Bit NIOS-II, a Layer 2 Ethernet switch can be implemented in a FPGA (Field Programmable Gate Array) ...

Traditionally, routers, which inspect layer 3, were considerably slower than layer 2 switches. In order to increase routing speeds, many "cut-through" techniques were used, which perform an ...