Flexible Wafer-level Packaging Methodology Allows Same Silicon Design to Be Offered in Wire-bond or Flip-chip Bump Interconnect Format MILPITAS, Calif., May 19 ...

with planar bump heights and the challenge of inline micro void detection at the Cu-Cu bond pad interface. Undetected voids can lead to wafer cracking and open electrical connections, resulting in ...

Additionally, the EchoScan ™ system is introduced for detecting voids as small as 1µm in wafer bonding applications, such as advanced hybrid bonding for Cu-Cu interconnects. Initial orders for the 3Di ...