The A8B40G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a time-interleaved successive approximation register (SAR) ADC, with 8-bit ...

The DCP-IP core is optimized to be used as a DAC and an SAR-ADC in a wide specification ... sources for the DNL performance of the discussed DCP topologies. Fig. 3 shows the modeled yield function of ...

National Engineering Research Center of Lower-Carbon Catalysis Technology, Dalian Institute of Chemical Physics, Chinese Academy of Sciences, Dalian 116023, Liaoning, China University of Chinese ...

Abstract: This document presents a CMOS image sensor (CIS) with a high-speed single slope ADC(SS-ADC) that has a novel high-speed counter and can reduce ... It uses a circuit and dedicated counter ...